Faculty at School of Engineering

Sheel Sindhu Manohar

Sheel Sindhu Manohar

Assistant Professor

School of Engineering


Contact Information

Dr. Sheel Sindhu Manohar is an Assistant Professor in the Department of Computer Science and Engineering at Shiv Nadar Institution of Eminence, Delhi NCR. His research interests lie at the intersection of computer architecture, hardware security, memory systems, and AI-driven system optimization. His current work focuses on hardware performance and secure computer systems.

He has also contributed to research on non-volatile memory architectures, including STT-RAM-based cache design, read-disturbance mitigation, cache block migration, and hybrid memory systems. His recent research further explores machine learning and reinforcement learning techniques for cache prefetching, memory hierarchy optimization, and performance-aware computer architecture.

Dr. Manohar has published in reputed venues including IEEE Embedded Systems Letters, ACM TECS, IEEE TCAD, GLSVLSI, and Journal of Systems Architecture. His broader research vision is to design secure, intelligent, and energy-efficient computing systems for emerging workloads.

Computer Architecture and Hardware Security

  • 2022: Ph.D., Computer Science and Engineering, Indian Institute of Technology Guwahati.
  • 2015: M.Tech., Information Technology, Indian Institute of Information Technology Allahabad.
  • 2012: B.Tech., Computer Engineering, Jamia Millia Islamia, New Delhi.

Assistant Professor at Shiv Nadar University from Aug, 2022 to present

  1. S. Nayak, A. Goyal, S. Sindhu Manohar, D. Sankar Banerjee and P. Das, "Enhanced Prefetching via Dynamic Multistep SARSA-Based Reinforcement Learning," in IEEE Embedded Systems Letters, vol. 18, no. 2, pp. 103-106, April 2026, doi: 10.1109/LES.2025.3574850.
  2. Manohar, S. S., & Kapoor, H. K. (2023). Capmig: Coherence-aware block placement and migration in multiretention STT-RAM caches. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42(2), 411–422. doi: 10.1109/TCAD.2022.3175242.
  3. Manohar, S. S., Mittal, S., & Kapoor, H. K. (2022). Coridor: Using coherence and temporal locality to mitigate read disturbance error in STT-RAM caches. ACM Transactions on Embedded Computing Systems. https://dl.acm.org/doi/10.1145/3484493
  4. Manohar, S. S., & Kapoor, H. K. (2019a). Dynamic reconfiguration of embedded-DRAM caches employing zero data detection-based refresh optimisation. Journal of Systems Architecture, 100, 101648. doi: 10.1016/j.sysarc.2019.101648
  5. Manohar, S. S., Agarwal, S., & Kapoor, H. K. (2019). Towards optimizing refresh energy in embedded-DRAM caches using private blocks. In Proceedings of the 2019 Great Lakes Symposium on VLSI (pp. 225–230). doi: 10.1145/3299874.3317995.
  6. Manohar, S. S., & Kapoor, H. K. (2019b). Refresh optimised embedded-DRAM caches based on zero data detection. In Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing (pp. 635–642). doi: 10.1145/3297280.3297340.

Dr. Sheel Sindhu Manohar’s ANRF project focuses on the early detection of ransomware and malware attacks using hardware-aware runtime monitoring. The project aims to break the traditional dependency on software signatures and post-infection analysis by using Hardware Performance Counters (HPCs) to capture low-level microarchitectural behavior during program execution.

The core idea is to monitor events such as cache misses, branch misses, instruction behavior, CPU cycles, context switches, and TLB activity to identify abnormal execution patterns caused by malware. These runtime traces are then analyzed using machine learning models for fast and accurate attack detection.

The project is titled:
“Breaking the Encryption Barrier: Early Detection of Malware Using Hardware-Aware Models.”

The broader objective is to build a lightweight, runtime, hardware-assisted security framework that can detect high-speed malware activities before severe system damage occurs.