Cadence Design Contest 2017 Runner up | Shiv Nadar University

Cadence Design Contest 2017 Runner up

Research
19 Mar 2018

project Titled "Implementation of Low Power FIR Filter Using Full Swing Gate Diffusion Input Technique" with B. Tech. Final Year ECE student Mr. Anmol Raj has secured II rank in all India Cadence Design Contest 2017  under the supervision of Dr Sonal Singhal

Most of the participating candidates in the contest were from the esteemed institutes like IITs, IISc, NITs, BITS, etc. There were  200 projects  participating in this contest. The filtration process was 3 tier. The top five projects were reached in final round of presentation.

Master’s Category

 

Winner

Institute Name

BITS Pilani

Project Title

Design and Implementation of Differential Power Analysis Attack Immune Encryption Circuit Based on Simon Block Cipher for Next Generation RFID Cards

Team Members

Harjap Singh Saini and Abhinav Garg

Guide

Dr. Anu Gupta

 

Runner-up

Institute Name

Indian Institute Science

Project Title

See-Through-Wall FMCW RADAR on PCB and Chip in S-Band

Team Members

Sachin G and Vysakh K

Guide

Prof. Gaurab Banerjee

 

Bachelor’s Category

 

Winner

Institute Name

BITS Pilani

Project Title

Design of DQPSK Demodulator for Implantable Bio-Medical Devices

Team Members

Vaibhav Garg and Neha Agarwal

Guide

Kavindra Kandpal

 

Runner-up

Institute Name

Shiv Nadar University

Project Title

Implementation of Low Power FIR Filter Using Full Swing Gate Diffusion Input Technique

Team Members

Anmol Raj

Guide

Dr. Sonal Singhal

 

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