Department of Electrical Engineering
Department of Electrical Engineering,
School of Engineering
Email Contact: email@example.com
Ph.D. (IIT Delhi, 2016) - "Design of Wireline Communication Receivers for Multi-Gigabit Data Rates"
Masters in Electronics and Communications (VLSI for communications), Thapar University
Technical Leader (TRND - I/O Group) STMicroelectronics
Technical Manager - (SERDES Group) Cadence Designs Systems
Analog and Mixed Signal Design
- Monga, S., Shouri Chatterjee, “An Inductorless Continuous Time Equalizer with Programmability for Gigabit links” IEEE MWSCAS’14.
- Monga, S.,” Adaptive driver with automatic sense and calibration in CMOS 40LP” IEEE SOCC 2013.
- Monga, S.,” High Speed Stress Tolerant 1.6 V - 3.6 V Low to High Voltage CMOS Level Shift Architecture in 40 nm” IEEE ISCAS 2012.
- Monga, S.; Kumar, V. “A 73μW 400Mbps stress tolerant 1.8V-3.6V driver in 40nm CMOS” ; ESSCIRC (ESSCIRC), 2011 Proceedings of the Digit Object Identifier: 10.1109/ESSCIRC.2011.6044896 , Publication Year: 2011, Page(s): 187 – 190
- Monga, S., “Input and Output buffer including a dynamic driver reference generator”, US Patent Pub. No: US 2011/0254591A1, 2011.US20110254591
- Monga, S., “An Adaptive Buffer”, US20130169311
Sushrant Monga has an experience of 11 years in the Semiconductor design with STMicroelectronics and Cadence Design Systems. He has an experience of 9.5 years with STMicroelectronics, where at TRND group he worked on I/O transceivers for multiple protocols and different speeds ranging from 200 Mb/s multi-purpose multi-voltage I/O to 8 Gb/s I/O’s for PCI 3.0 protocol. He had an extensive work experience to develop LDO, s, I/O’s and equalizers (receiver’s analog front-ends) in all the upcoming CMOS technologies. His work involved consultancy and design for adaptive I/O’s, general purpose I/O design, calibration and compensation blocks for the PVT, DDR I/O (for generations DDR2,DDR3 , and DDR4 ), LVDS, Sub-LVDS, LP(Low power)-I/O’s etc. He moved to Cadence design Systems for working in the SERDES team involving the design of multi-Gb/s as Technical Manager in the transceiver designs. He was working in 28nmn and 16 FF CMOS technologies for the design of serial-link receivers for 10 Gb/s links. This involved designing the adaptive equalizers, Phase recovery loops, and ensuring the hi-fidelity output for the transceivers for a given application.